The complexity of modern integrated circuitry continues to increase at a dramatic rate. Modern integrated circuits (ICs) include millions of transistors contained on a single substrate. In order to create the millions of transistors on the substrate, the size of each transistor has decreased dramatically. Thus, at present, a single IC occupies less area, operates more quickly, and consumes less power than ever before. However, with the increase in transistor numbers on each IC, the likelihood that at least one transistor contained on the IC malfunctions after fabrication also increases. Thus, various testing methods have been developed in the state of the art to verify the operation of ICs after fabrication but prior to sale.
One testing methodology according to the state of the art involves providing a certain set of inputs to the IC over many clock cycles, reading the outputs generated by the inputs, and comparing the outputs to expected results. When the outputs fail to correctly correspond to the expected results, the IC has improperly functioned. However, in order to test each particular internal logic portion of the IC, a huge number of variations in inputs must be provided. When the output is not the correct output when designing the IC, a diagnostic engineer still must spend a significantly large amount of time identifying which malfunctioning transistor or set of malfunctioning transistors caused the error. Thus, in modern ICs, the ability to test internal logic with standard functional or operational vectors is no longer cost efficient. The transistor-to-package pin ratio is typically too large to successfully verify the internal structure of the chip in a reasonable amount of vectors or test time.
Furthermore, many techniques that have been used to test and verify densely packed board designs cannot be used within the operation of the IC, because there is no direct access to many of the circuits within the packaged and sealed IC.
As an alternative to prior testing techniques, the test technique of internal embedded scan design has become a cost effective solution to test the operation of ICs. Scan design is accomplished by altering the structure of standard flip-flops and latches (storage elements) within the IC into scan flip-flops and latches by providing a second alternate scan input for scan data parallel to the functional data input. The alternate input for scan data is generally implemented by placing a multiplexer in front of the standard input that selects either scan data or functional data. These “scannable” elements are then connected together in a serial shift register fashion by connecting the output of one element to the scan input of a next element via a “scan chain”. The scan chain can load and unload internal IC state information by allowing scan data to be transferred from one element to another on each active clock pulse (edge) when a scan enable signal is asserted.
The operation of ICs employing scan design may switch from the scan mode to the system mode at any clock cycle. In this fashion, a particular scan data sequence may be loaded into the scannable elements during scan mode. Such scan data sequence is a sequence intending to produce a particular logic function outcome from the logic functions in the IC. Once the scan data sequence is loaded, the operation of the IC is switched to system mode for a single clock cycle, and the resulting system data is captured in the scannable elements. The IC is then placed in scan mode and clocked until the data is received at a serial output pin. The received data is then compared to expected results to verify the operation of the logic circuitry for the particular case. In this fashion, the operation of at least a portion of the logic circuitry in the IC may be verified even though this portion of the logic circuitry is internal to the IC and difficult to access directly via external pins of the IC.
Due to the fact that modern semiconductor chips, especially processor chips, comprise a plurality of electronic elements, one is also faced with the problem of very high power consumption. Therefore, it is necessary to reduce the power consumption of such semiconductor chips. One efficient method for reducing static power consumption in CMOS circuits is to switch-off supply voltage. Such approach is called power gating if it is done on-chip. Typically, power may be gated for several individual sub-blocks. A method according to the state of the art uses separate power domains to subdivide the semiconductor chip. Each power domain has a separate power supply or some way to turn off its local power. As many transistors as possible may be switched off, or their voltages may be reduced.
For testing purposes of the chip, all or part of the storage elements of each power domain are interconnected to a scan chain. Each scannable storage element comprises a scan input and a scan output. The scan chain includes a plurality of connections between the scan output of one storage element and the scan input of the next storage element. The scan chain is a serial line moving a data bit into each storage element according to a predetermined pattern scheme. During testing the scan chain has the functionality of a shift register.
If such a power domain is switched off or if the circuit's voltage is reduced, then a scanning process is not possible on the power domain, since the logic inside the power domain is not functional. Hence, the entire scan chain is interrupted, and it is no longer possible to scan the storage elements on the active power domains of the semiconductor chip.
In the state of the art, a solution to this problem is to activate all power domains with storage elements to be scanned. However, such technique results in a huge power consumption peak that may be not be supported currently by the system. Moreover, the activation of all power domains for scanning purposes takes a relatively long time. This method is already used during bring-up, where no or less cooling constraints are present and where no power reduction techniques need to be applied that could impact the functionality of the scan chain. In U.S. Publication No. 2006/0168487, an alternative is provided in which all of the registers have shadows that hold the same contents and are always powered. In such a way, the scan-out pattern is preserved independent of circuit state. No multiplexer is required in scan chain.
Another solution in the state of the art is to subdivide each scan chain into independent scan chain portions at each power domain. However, such technique requires additional wires running from and to the scan engine. Thus, the complexity of the scan structure and its verification is increased. If there is only one storage element in the wrong domain, then the scan chain is interrupted. In the worst case, the configuration chain for the power controller is interrupted, preventing activation of the power domain with the badly-wired storage element. Moreover, such solution requires a change to the chip masks and a remanufacturing of the semiconductor chip. Furthermore, in this solution the user must activate the power domain to be scanned beforehand, and more overhead must be added to the software. An alternative to circumvent such disadvantage is to apply a multiplexer to the scan chain to bridge the power gated portions within the scan chain (see FIGS. 1A and 1B and accompanying description herein). However, the drawback of such approach is the creation of scan patterns of varying length depending on the current power gating status. Additional status bits within the scan chain can signal the changes in the scan chain. However, read-out circuitry would have to adapt to a large variety of possible scan chain lengths, and currently chip tests do not support state-dependent scan chain lengths.